The present invention is directed to semiconductor device packaging and, more particularly, to a semiconductor device with redistribution connections between internal contacts on one or more semiconductor dies and external contacts on an active face of the device package.
Semiconductor dies are packaged in order to provide electrical connections between the die and external package contacts and to protect the die against mechanical and environmental stresses. Continued progress in reduction of the size of the semiconductor dies and increased functionality and complexity of the integrated circuits formed on the dies requires size reduction of the packaging with the same or greater complexity of the electrical connections with external circuits.
As part of the packaging or assembly process, the semiconductor dies are embedded or encapsulated with a molding compound. The electrical contacts for connection with external circuits are exposed at the active face of the package and connected internally with electrical contact pads on the semiconductor die. The external contacts may be a ball grid array (BGA) or a land grid array (LGA), for example. Various techniques are available for connecting the exposed, external electrical contacts of the package with the internal contacts of the embedded semiconductor die.
Minimum values are specified for the size of the individual exposed electrical contact surfaces at the active face of the device and for the spacing between adjacent electrical contact surfaces. Such specifications necessitate a compromise between the overall size of the active face of the device and the number of individual electrical contact surfaces.
In a technique known as Redistributed Chip Packaging (RCP), a redistribution layer provides interconnections between the internal set of contacts on the semiconductor die and the exposed device set of contacts at the active face of the device, to route signals and power and ground connections. In one technique of production of embedded RCP devices, singulated dies are placed temporarily with their active faces on a substrate. The dies are embedded with a molding compound and then released from the substrate, forming a panel. The panel can then be processed by wafer processing techniques to build up a redistribution layer that ‘fans out’ the internal contacts of the die set to the device set of exposed contacts, which covers an area greater than the area of the active face of the die. The redistribution layer may be built up by depositing successive layers of insulating material with electrical interconnectors in one or more layers, which may have vias providing connections between layers, separated from each other by insulating layers. The interconnections are typically deposited by electroplating techniques, and patterned using batch process lithography. Connection with signal input/output and power and ground pads on the active faces of the dies may be made during electro-deposition of the interconnectors and vias. The devices are singulated after completion of the redistribution layer.
The semiconductor device may include a metallic member extending beside the semiconductor die towards the edge of the semiconductor device and also embedded in the molding compound. Such a metallic member may be part of a ground plane, for example. In use of the device, such a ground plane may be connected or capacitively coupled to ground or to a stable voltage source to shield the device from electromagnetic interference caused by external circuits or sources of noise, or from unwanted electromagnetic coupling between adjacent circuit elements. Difficulties in ensuring manufacturing compatibility of such an embedded metallic member with the redistribution layer need to be overcome.